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Résumé:
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Increasingly complex embedded systems are being designed onto single chip systems that contain multiple parallel processing elements and memories. The design and implementation of these
multiprocessor on-chip architectures is time consuming, delaying the time to market. Manual hardware design is also error-prone, requiring careful verification and further delaying the time to market. In order to solve the aforementioned problems, an open source VHDL generation tool called SING was created to design and implement heterogeneous multiprocessor system-on-chip designs. The requirements for the tool which are partially or fully addressed are: 1. use of existing and open-source components, 2.
automated generation of VHDL, 3. Eclipse framework, and 4.
simulation capabilities. The tool comes with a graphical user interface (GUI) and an application programmer interface (API),
and exports VHDL with accompanying documentation in accordance with the WISHBONE B.3 standard. The exported VHDL can then be prototyped on an FPGA platform. Even though some similar tools exist, there are not many papers that
present detailed internal design of the tools. We believe that our
detailed description of the object oriented implementation will be
helpful to designers of similar systems. |
