| dc.contributor.author |
Shapiro, Daniel |
|
| dc.contributor.author |
Bolic, Miodrag |
|
| dc.date.accessioned |
2011-02-24T16:21:39Z |
|
| dc.date.available |
2011-02-24T16:21:39Z |
|
| dc.date.created |
2011 |
en_US |
| dc.date.issued |
2011-02-24 |
|
| dc.identifier.uri |
http://www.site.uottawa.ca/~dshap092/ |
en_US |
| dc.identifier.uri |
http://hdl.handle.net/10393/19799 |
|
| dc.description.abstract |
The three Instruction Set Extension (ISE) enumeration algorithms
described in this paper are Subgraph Enumeration
(SE), Subgraph Removal (SR), and Lucky Subgraph Removal (LSR). SE exhaustively enumerates all convex subgraphs of a
dataflow graph. SR iteratively finds the highest gain subgraph
and then locks the related nodes out of the solution space for the next iteration of the search. Finally, LSR represents our
tunable approach where both SE and SR are used to trade compiler execution time for solution quality in a hardware constrained design space. In this paper we present the mechanics behind these three ISE enumeration algorithms, and
an instruction selection algorithm compatible with all three approaches. |
en_US |
| dc.description.sponsorship |
NSERC |
en_US |
| dc.language.iso |
en |
en_US |
| dc.subject |
Instruction set extension |
en_US |
| dc.subject |
instruction enumeration |
en_US |
| dc.subject |
instruction selection |
en_US |
| dc.subject |
configurable processor |
en_US |
| dc.subject |
ASIP |
en_US |
| dc.subject |
ISE identification |
en_US |
| dc.title |
Improved ISE Identification Under Hardware Constraint |
en_US |
| dc.type |
WorkingPaper |
en_US |
