VLSI systolic array architecture for the computation of the discrete fourier transform.

VLSI systolic array architecture for the computation of the discrete fourier transform.

Affichage abbrégé

dc.contributor.author Beraldin, Jean-Angelo. en
dc.date.accessioned 2009-03-20T14:00:45Z
dc.date.available 2009-03-20T14:00:45Z
dc.date.created 1986 en
dc.date.issued 2009-03-20T14:00:45Z
dc.identifier.citation Source: Masters Abstracts International, Volume: 40-07, page: . en
dc.identifier.isbn 9780315332812 en
dc.identifier.uri http://hdl.handle.net/10393/5042
dc.publisher University of Ottawa (Canada). en
dc.subject.classification Engineering, General. en
dc.title VLSI systolic array architecture for the computation of the discrete fourier transform. en
dc.type M.A.Sc.Thesis (M.A.Sc.)--University of Ottawa (Canada), 1986. en

Fichier(s) constituant ce document :

Fichier(s) Taille Format
ML33281.PDF 3.204Mb application/pdf Voir/Ouvrir

Cet article est disponible dans les collections suivantes

Affichage abbrégé


Nos coordonnées

Pavillon Morisset (carte)
65, rue Université
Ottawa ON Canada
K1N 6N5

Tél. 613-562-5800 (4563)
Fax 613-562-5195

ruor@uottawa.ca